A low noise and low power 3-GHz 64~127 Multi-Modulus Frequency Divider implementation using BiCMOS technology

This paper presents implementation of a high speed, low noise and low power frequency divider based on current mode logic and cascade connection of divide-by-2/3 cells for high division range. The proposed divider is optimized for high frequency and low power operation. Integration of the proposed divider in a frequency synthesizer is an attractive option for the ultra-low power carrier signal generation in coherent wired and wireless communication systems. A prototype has been implemented in 0.24μm SiGeBiCMOS technology. The operating frequency is 3 GHz; the divide ratio is 64/127 with step of 1 with 2.5V power supply and current consumption is 1.5mA occupying 0.06mm 2 chip areas. The modulus may be integer or fractional.